Inside multi-tiered semiconductor waveguide

What changes in this design

Light-guiding channels on chips are typically built as a single block of uniform width and height, with any nearby heating element laid out as one plain strip running above it, not shaped to match the channel's profile.

Here the channel itself steps down in size, a narrow tall section next to a wider shorter one, and the heating layer above it is split to match, with one heating strip over the narrow section and two more positioned on either side over the wider section.

Seeing how closely the heater layout tracks the channel's changing shape gives a sense of how carefully engineers fit control elements into the small, layered spaces inside a modern chip, where every part has to share room with its neighbors.

A Material That Won't Hold Still

Light moves through a photonic chip along waveguides: grooves of silicon and glass a few hundred nanometers wide, cut to bend a laser beam the way a wire bends current. Silicon is the workhorse material for this job because it's cheap and well understood, but it has a habit that makes engineers nervous. Its refractive index drifts with temperature roughly seven times faster than silicon nitride, the other waveguide material commonly used alongside it. Run one waveguide a few degrees warmer than its neighbor and it stops being the same waveguide: it starts steering light by tiny fractions of a degree, enough on a busy data link to break the signal.

Reading into this filing, I hadn't expected heat to be treated less like a hazard and more like a material to be shaped in its own right. That's the premise behind nearly every heater sitting on a modern silicon photonic chip: a resistive strip laid close to a waveguide, constantly nudging it back to the temperature the design assumes. Multiply that by the thousands of waveguide segments doing this on one chip carrying a datacenter's traffic, and thermal tuning stops being a footnote. That, to my eye, is one of the largest power costs on the chip.

Two Tiers, Three Heaters

One answer to that cost showed up in a patent published on September 3, 2026, filed the previous April. Titled Multi-Tiered Semiconductor Waveguide And Multi-Tiered Waveguide Heater, it describes a waveguide built in two steps rather than one: a narrower, taller first tier sitting on a base dielectric layer, wrapped by a wider, shorter second tier, the whole assembly covered in cladding. Above that sits a matching heater structure: one heater tier positioned directly over the narrow first tier, and a second pair of heaters straddling the wider tier on either side of the first.

Filed under application number 19/659,084 and assigned to Taiwan Semiconductor Manufacturing Company, the filing doesn't spell out in so many words why three heaters beat one. The geometry suggests an answer anyway: shape the heat source to match the shape of the thing being heated, rather than blanket-warming a waveguide that has two different profiles doing two different jobs.

Fifty Filings to Intel's Twenty-Six

This filing didn't arrive alone. Patent-count data compiled from Patentfield, covering January 2015 through July 2025, shows Taiwan Semiconductor and Intel filing US silicon-photonics patents at close to the same rate in 2023, 46 against 43, before Taiwan Semiconductor pulled well ahead in 2024, filing roughly 50 to Intel's 26. The company has said this work feeds a platform called COUPE, short for Compact Universal Photonic Engine, which bonds electronic and photonic dies together and is aimed at mass production in 2026. Its stated customers include the biggest maker of AI accelerator chips and a major networking chip maker, both chasing faster optical links between servers.

Counting patents this way tells you, in my reading, how hard a company is racing, not whether any single idea works. This filing carries no test data and no figures on power saved. It is a claim staked on a shape, filed early enough to matter if the shape turns out to be the right one.

Other Labs, Other Fixes

Other groups chasing the same heater-efficiency problem aren't restacking anything. Cutting voids into the dielectric around each heater element is the fix tried in a separate application, filed roughly six months earlier: trapping heat rather than reshaping its source. Academic work published in March 2025 and revised that June went further: removing the substrate from underneath the waveguide entirely, across a full 300-millimeter wafer, and reporting efficiency gains of about 5 times for a compact disk-shaped modulator and roughly 40 times for a Mach-Zehnder phase shifter, achieved by taking material away rather than adding layers.

A chip designer called Ayar Labs has published a heater efficiency record of its own: 3.8 microwatts per gigahertz, across a 524 gigahertz tuning range covering more than 50 degrees Kelvin of temperature drift. It got there with a control circuit that tunes based on a chip's own bit statistics, not with any new heater shape at all. Three separate groups are attacking the same milliwatt-sized problem from three completely different directions, I find, with no sign yet of agreement on where the power savings actually live.

The harder half of the problem

My doubt about this filing isn't about the physics. Nothing about the tiered geometry looks wrong to me; it's a sound response to a real, well-documented problem. It's about where that problem sits on the list of things actually holding this technology back. A paper submitted in March 2026 argues that the industry keeps treating co-packaged optics as something to be solved one device at a time, a better modulator here, a more efficient heater there, when the real obstacles sit one level up: how these chips get packaged at scale, how heat gets managed across a whole system rather than one waveguide at a time, and whether a design can be serviced and standardized the way a datacenter operator needs it to be.

We won't know for some time whether this particular heater stack ships in a real product, let alone whether it moves the industry's power numbers by an amount any customer would notice. What's clear from reading the surrounding research is that a great deal of well-funded engineering is aimed at a target that at least one credible paper says is the wrong one, not because the engineering is bad, but because the bottleneck, at least by that paper's account, was never really sitting in the heater at all.

Sources

Reporting for this piece drew on the published filing and the references below.

1. TSMC surpasses Intel in US silicon photonics patents as chip industry ramps up initiatives (DIGITIMES)
2. Silicon Photonics in the Spotlight: TSMC Lifts the Curtain on COUPE at SEMICON Taiwan (TrendForce)
3. OFC50: The Era of High-Speed Silicon Photonics Has Arrived (tspasemiconductor Substack)
4. Heterogeneous Integration Technology Drives the Evolution of Co-Packaged Optics (MDPI/PMC)
5. U.S. Patent Application for Silicon Photonic Integrated Circuits with Enhanced Thermal Isolation of Heater Elements (Justia)
6. Highly uniform thermally undercut silicon photonic devices in a 300 mm CMOS foundry process (arXiv)
7. A 45nm CMOS-SOI Monolithic Photonics Platform with Bit-Statistics-Based Resonant Microring Thermal Tuning (Ayar Labs)
8. 3D optoelectronics and co-packaged optics: when solving the wrong problems stalls deployment (arXiv)

The record, briefly. US20260259367A1, “Multi-Tiered Semiconductor Waveguide And Multi-Tiered Waveguide Heater” Describes an integrated chip with a base dielectric layer and a multi-tiered semiconductor waveguide layer having a narrower, taller first tier and a wider, shorter second tier, covered by a cladding layer and a multi-tiered conductive heater layer with one heater tier over the first waveguide tier and a pair of heater tiers over the second tier on opposite sides of the first.

More angles on this

• Waveguide For Display Panel Makes a Small Case for Better TimingAnother reading from the same G02B classification family, optical elements, systems or apparatus.
• When Flexible Light Guides Meet at the SeamAnother reading from the same G02B classification family, optical elements, systems or apparatus.
• CPC G02B: Optical elements, systems or apparatusThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
• CPC G02F: Optical devices or arrangements for the control of light by modification of the optical properties of the media of the elementsThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
• Why a Deliberately Weaker Signal Can Make a System More HonestAnother reading of a record filed by the same applicant, Taiwan Semiconductor Manufacturing Company.

Read around this one:Public patent recordUSPTO published figure