In-Memory Computation System Using A Segmented Memory Architecture With Marks a Pause Worth Noticing

What changes in this design

Without more detail about a system, a reader might picture one shared memory grid serving one calculation at a time, with all of its assigned pieces belonging to that task.

Instead, a control circuit assigns separate groups of memory cells, input lists, number values called weights, and vertical output wires, called bit lines, to two independent calculations. The two calculations are carried out at nearly the same time.

This is worth knowing because the separate cell groups and wires are not all for one task. They are assigned to two calculations that proceed together in the same grid.

March 9, 2023

On March 9, 2023, I could have mistaken the news about Mythic for a routine financing item. The analog compute-in-memory company had raised more than $170 million, built a 25 TOPS flash-based matrix processor, and then ran out of capital in November 2022. A $13 million rescue kept it alive and redirected it toward defense work. That failure corrects the usual patent-reading instinct, which is why I start there. A clever way to multiply matrices inside memory is not, by itself, a business.

It must also survive manufacturing, software, precision limits, and a customer's reluctance to be first. That is why a filing published on August 27, 2026 caught my attention. It comes from STMicroelectronics, which is pursuing phase-change memory for automotive microcontrollers. That industrial footing makes this, I think, a more consequential persistence story than another laboratory demonstration, even though it does not prove the computing architecture is ready for a vehicle.

The Stellar P6

The evidence I found is not a shipping tally. In April 2025, the company said its first xMemory device, Stellar P6, was expected to begin production later that year. Contemporary coverage described it as a 28 nm automotive microcontroller with proprietary phase-change memory, and the company said that memory could offer more than twice the capacity of flash and rival embedded nonvolatile memories. Those are company claims, not an independent audit.

Still, I find the context important. A memory program aimed at automotive microcontrollers faces a different set of demands from a research board: endurance, cost, qualification, and long-lived software support. A production plan is not, in my view, evidence that in-memory computing is already in a car. But it gives this patent family a real manufacturing context, which is more than many analog-computing proposals ever receive.

Two jobs, one matrix

The new publication, US20260253636A1, is not a sudden invention. It was filed on April 17, 2026 as a continuation of an application filed September 1, 2023, and it appeared on August 27, 2026. That matters to me: this is a company continuing to prosecute a particular architecture, not announcing a brand-new direction.

The architecture divides a memory-cell matrix into separate cell groups. Each of two matrix-vector computations gets its own input vector, weights, and output bit lines, and the operations are carried out substantially simultaneously. Local memory-array selection is part of the control, while the associated analog-to-digital conversion counting is scaled to each operation's matrix dimensions. The architecture looks to me like an effort to let one physical array handle two independent jobs without making one wait behind the other. It is a sensible scheduling idea. It is not evidence of a finished product.

Three or four bits

In-memory computing has not yet made arithmetic behave the way ordinary software expects, which is why I keep that distinction in view. IBM's 2023 HERMES research chip put 64 analog phase-change-memory cores, each a 256x256 crossbar, on one die. The reported chip used more than 16 million PCM devices and reached 63.1 TOPS peak performance. Across all 64 cores, however, its effective matrix-vector-multiply precision was only 3 to 4 bits.

The results were encouraging and constrained at once. A Flickr8k captioning run matched its software baseline exactly, and a CIFAR-10 result reached 92.81 percent accuracy. But the researchers also said hardware-aware training was needed to approach software-equivalent accuracy. That deserves to be taken seriously, I think. It means the system's value depends not merely on a fast array, but on whether models, calibration, conversion circuits, and developers can live with its imperfections.

Where the risk actually sits

The central question is not, I think, whether a matrix can be multiplied in a phase-change-memory array. Research has shown that it can, and this filing lays out a more concurrent way to arrange two such calculations. Nor is the central question whether phase-change memory has an industrial use outside the lab. The automotive program gives that question a concrete setting, even if the material I reviewed does not confirm production volume.

The risk sits at the seam between those facts. Analog behavior, per-job data conversion, accuracy, software support, yield, and economics have to hold together after a demonstration ends. The continuation tells me STMicroelectronics has not dropped that problem after almost three years of prosecution. Persistence is, to me, evidence of interest, not proof of arrival. That distinction is why I will keep watching this family. The ordinary memory business may be the reason its stranger computing ambition deserves attention.

Sources

Reporting for this piece drew on the published filing and the references below.

1. US20260253636A1 patent record
2. In-Memory Computation System Using A Segmented Memory Architecture With Local Memory Array Selection
3. US 2025/0078922 A1 parent publication
4. AI chip startup Mythic rises from the ashes with $13M, new CEO
5. IBM develops a new 64-core mixed-signal in-memory computing chip
6. Analogue in-memory computing coming of age
7. STMicroelectronics Future-proofs the Development of Next-gen Cars with Innovative Memory Solution for Automotive Microcontrollers

The record, briefly. US20260253636A1, “In-Memory Computation System Using A Segmented Memory Architecture With Local Memory Array Selection For Simultaneously Performing Multiple Independent Operations” A memory-cell matrix has row word lines and column output bit lines. A control circuit assigns separate cell groups, input vectors, weights, and output bit lines to two matrix-vector in-memory computations that are substantially executed simultaneously.

Identity details. The saved title-page transcription needs review, so names are not repeated here. Check the official published title page.

More angles on this

• The Useful Quiet Room Beside MemoryAnother reading from the same G11C classification family, static stores.
• When a Pair Does Not MatchAnother reading from the same G11C classification family, static stores.
• CPC G11C: Static storesThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
• CPC G06F: Electric digital data processingThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
• Orchard Math Has Entered Its Managing EraAnother reading from the neighbouring G06T classification family, image data processing or generation, in general.

Read around this one:Public patent recordUSPTO published figure