Objects

Keeping Time Across a Stack

A modest timing patent arrived as SK hynix's AI memory boom hit a peak, revealing how much the next stack may depend on a different kind of connection.

Clay-diorama editorial illustration related to Memory Device Configured To Input And Output Data.

What changes in this design

A reader might picture memory hardware as one flat chip, with timing and data handling happening in the same place.

Here, the upper core chip sends data to the base chip without matching its timing. The base chip turns even and odd read signals into slower timing beats, makes two output timing cues, and sends those cues through signal paths.

That division of roles changes the picture from a single chip to a stack whose data and timing are handled in different places. It also identifies the base chip as the one that produces the output timing cues.

August 27, Indiana

On August 27, 2026, SK hynix broke ground in West Lafayette, Indiana, on a high-bandwidth-memory packaging plant expected to cost more than $4 billion. Its finalized $458 million federal grant came with a target of HBM4E mass production in the third quarter of 2029. A factory floor makes this filing's scale easier to feel, so I start there.

That day, an application published under the plain name Memory Device Configured To Input And Output Data. US20260253631A1, assigned to SK hynix, remains pending; it claims a February 26, 2025 priority date and was filed June 19. The shared date isn't proof to me that the plant and paperwork are connected. The same fact I see in both is this: memory has become physically expensive.

The base chip

The application reads to me as a timing problem in circuit language. A base chip sits below vertically stacked core chips. It divides even and odd read signals into clocks, combines them into two output-strobe signals, sends them up set paths, and gets data back through other paths. This is not a new memory cell. It is a way to organize traffic when several layers move together.

That matters to me. The description locates coordination near the stack, with different path lengths in play. It is not an HBM4 product announcement or a promise of a datacenter breakthrough. For scale, the HBM4 standard published in 2025 allows up to 2 TB/s per stack across a 2,048-bit interface and 32 channels. Whether this application will be part of that standard isn't something I assume. That scale lets me see its timing problem more clearly.

The Nasdaq sale

By publication, that work belonged to a company having an unusually good year. SK hynix's reported 2025 operating profit was 47.2 trillion won, above Samsung's 43.6 trillion won - the first time its annual operating profit reportedly exceeded its rival's. In July 2026, its Nasdaq depositary-receipt sale raised $26.5 billion, the largest US share sale by a foreign issuer. Those figures are proof to me that signal timing can sit beneath a very loud market.

The boom is narrow. About 65% of SK hynix's 2025 revenue reportedly came from the United States, driven by AI infrastructure. Pricing is unsettled: one forecast warned of double-digit 2026 HBM average-selling-price drops as supply growth outpaced demand; another said HBM4 premiums could lift averages. Those conditions make a humble control scheme worth watching, I think. It is timing work in a business that cannot depend on one price story.

Four hundred layers

A boundary is what I want to keep in view. The application places a base chip beneath vertically stacked core chips, but it does not establish that the design is the PUC, or peripheral-under-cell, NAND arrangement SK hynix called 4D NAND. The resemblance is structural, not identity. Yet PUC shows why engineers put support circuitry underneath: its 96-layer version claimed a 30% smaller die and 49% better wafer productivity.

Then the stack got taller. The teardown I found of a 128-layer PUC part measured 147 stacked gates, 87.1% vertical cell efficiency, and about 8.15 gigabits per square millimeter of TLC density. But reports say that beyond roughly 400 NAND layers, pressure can damage the underlying peripheral region. The reported response is wafer-to-wafer hybrid bonding: build cells and peripheral circuitry separately, then join them.

This is where I reject a triumphal reading. Samsung reportedly licensed YMTC's hybrid-bonding patents for its roughly 430-layer V10 NAND. Reporting also puts much of the relevant patent position in a few hands, including YMTC. Today's lead in stacked memory doesn't remove the engineering and licensing problem at greater layer counts.

The open question

US20260253631A1 is not, to me, a verdict on who wins memory. The application is, to me, evidence of boom-time work: send timing signals upward and data back along separate paths. Its value, if any, depends on whether it fits products customers buy, not on a fundraising or groundbreaking.

The harder question is whether the next advance rewards this tightly managed stack or forces a sharper split between cells and support circuitry. The pending application can't answer it for me. The pressure, I can say, arrives before the factory opens: prices may soften, revenue is concentrated in one country, and the next layer of progress may run through patents held elsewhere.

Sources

Reporting for this piece drew on the published filing and the references below.

The record, briefly. US20260253631A1, “Memory Device Configured To Input And Output Data” A memory device includes a base chip that generates division clocks from even and odd read signals, synthesizes first and second output strobe signals, and outputs them through signal paths; a vertically stacked core chip outputs data asynchronously to the base chip.

More angles on this

A Sideways Reading of Split StaircasesAnother reading from the same G11C classification family, static stores.
CPC H10B: Electronic memory devicesThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
CPC H10W: Generic packages, interconnections, connectors or other constructional details of devices covered by class H10The official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
Liquid Cooling Heat Dissipation Device For Multi-Disk Drive System Marks a Pause Worth NoticingAnother reading from the neighbouring G11B classification family, information storage based on relative movement between record carrier and transducer.
The Clip Needs Its ContextAnother reading from the wider H04N classification family, pictorial communication, e.g. television.

Read around this one:Public patent record USPTO published figure