Field Notes

Memory Circuitry And Method Used In Forming Memory Circuitry Questions the Default Arrangement

An obscure memory filing shows why the race to pile NAND cells upward now turns on manufacturing, equipment access, and where capital goes.

Clay-diorama editorial illustration related to Memory Circuitry And Method Used In Forming Memory Circuitry.

What changes in this design

The record does not state how memory circuitry is ordinarily formed, so it does not establish a conventional layout for comparison.

This method forms two stacked sections of alternating conducting and insulating tiers. Strings made of channel material are directly joined vertically, and an insulating tier sits between the lower and upper sections.

It gives a clear picture of the construction being addressed: layers that alternately carry electricity or block it, assembled above and below an insulating divider with vertical links. A performance result is not stated.

232 layers in November

The number that stopped me was 232. In November 2022, analysts found a 232-layer NAND chip from YMTC on the market. It was ahead of a 236-layer part that appeared the same month and another 238-layer part planned for 2023. The number mattered because NAND flash had already stopped winning by making its cells smaller. By 2015, planar flash had reached roughly 15-16 nanometres, and leakage made further scaling increasingly punishing. The industry began stacking cells vertically instead.

By October of that year, a U.S. export rule barred equipment for making 128-layer-or-greater 3D NAND in China. It was not written about one chip, but its threshold made a brutal contrast with 232. Layer counts had become more than a technical bragging right: they helped decide which factories could keep climbing. The familiar story says there is a race. This was, to my eye, the point at which the race acquired a gatekeeper.

The hole that bends

3D NAND is built around vertical strings, long channels that pass through layers of memory cells. The deeper the hole that must be etched for one of those strings, the harder it is to keep the walls true. A 2022 account of Micron's roadmap identified the practical failure: sides of very deep holes can distort, and distorted holes can keep cells from operating properly. Two-deck string stacking is the workaround. Build a lower deck, build an upper deck, then make the channels meet.

That makes the central difficulty much less glamorous than the finished chip: getting a pair of structures to behave as one without losing usable devices in the process. The industry's earlier pivot from planar NAND was driven by physics. Its newer puzzle is manufacturing discipline, repeated hundreds of layers at a time. I kept coming back to that distinction, because the next layer is only valuable if the whole stack can be made reliably.

The seam in the stack

US20260253639A1 appears here, in the seam between those two decks. It describes lower and upper stacks of alternating conductive and insulating tiers, with channel-material strings coupled directly from one to the other. An insulating tier sits between them. That sounds narrow, in my view, because it is narrow: the application does not announce a consumer product, name a layer count, or promise a faster drive. It seeks claims around a way of forming the join that lets a vertical string continue across separately constructed stacks.

The closest public family member, filed in August 2022 and published in February 2024, carries the same title and names Micron as assignee. A sibling patent granted in July 2025 addresses other pieces of the same build, including stair-step wordline access and spacer masks. Taken together, they suggest a company building claims around not merely the tall tower but the joints, masks, and access routes that determine whether it can be manufactured. That is what a patent thicket looks like from inside: many claims around one production platform.

Where the investment goes

That protective work is landing during an awkward split in the memory business. In fiscal 2025, Micron reported $28.58 billion in DRAM revenue and $8.50 billion in NAND revenue. Two years earlier, those figures were $10.98 billion and $4.21 billion. The difference does not prove how the company will spend its next dollar. It does show why a patent meant for NAND arrives while AI demand has made DRAM and high-bandwidth memory the more rapidly expanding side of its business.

A May 2026 market report adds the sharper context: major suppliers cut NAND output in the second half of 2025 and redirected capital expenditure toward AI-driven DRAM and HBM, while new NAND fab capacity was not expected before late 2027 or 2028. The filing alone cannot, in my view, tell us how its assignee will allocate capital. But it supports a less celebratory reading: process patents can preserve options while production growth slows. Keeping a route to taller NAND is not the same thing as paying to take it at full speed.

The harder half of the problem

Layer count is therefore a bad standalone scoreboard. Some competitors are pursuing hybrid bonding, joining separately prepared wafers rather than relying on monolithic string stacking. That route may make the next climb less dependent on one extraordinarily deep channel hole. YMTC's 232-layer Xtacking part makes the point without settling it: an architecture can reach the market early, yet access to equipment can still change the competitive equation overnight. I do not read this filing as proof that one stacking method has won.

The harder half of the problem is whether a stack can be made reliably, in volume, with tools that a factory can obtain and capital that management will actually commit. This filing matters because it documents a serious answer to one part of that problem: how to bridge two NAND decks. It cannot answer the other part. The stack has to survive the factory, the market, and policy constraints on equipment. That, more than another impressive layer number, is where the race will be decided.

Sources

Reporting for this piece drew on the published filing and the references below.

The record, briefly. US20260253639A1, “Memory Circuitry And Method Used In Forming Memory Circuitry” A method forms a memory array with lower and upper stacks having vertically alternating first and second tiers, directly vertically coupled channel-material strings, and an insulator tier between the stacks; first tiers are conductive and second tiers are insulative in a finished-circuitry construction.

More angles on this

Shift Register Unit, Driving Method Thereof, Display Substrate And Display Marks a Pause Worth NoticingAnother reading from the same G11C classification family, static stores.
In-Memory Computation System Using A Segmented Memory Architecture With Marks a Pause Worth NoticingAnother reading from the same G11C classification family, static stores.
CPC G11C: Static storesThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
CPC H10B: Electronic memory devicesThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
A metal-MXene sandwich, and the quiet work of putting layers in the right orderAnother reading from the neighbouring H10W classification family, generic packages, interconnections, connectors or other constructional details of devices covered by class H10.

Read around this one:Public patent record USPTO published figure