Objects

Wake Up, Then Wake Everything Up

What I found was two Chinese chip makers staking claims over DRAM's first moments, when power-up choices can shape reliability.

Clay-diorama editorial illustration related to Memory Devices, Operation Methods Of The Memory Devices And Memory Systems.

What changes in this design

A reader might otherwise assume that a memory device simply becomes ready as soon as it is turned on.

This record says that, during startup, one built-in part directs another to refresh every memory cell at least once.

That detail helps a reader see that the device's preparation includes a full pass through its tiny storage cells, not merely turning the power on.

8,192 rows

Before a phone opens its first app or a server takes its first request, its DRAM has already had to account for charge leakage. Each cell holds charge in a tiny capacitor, and that charge fades. A memory chip's power-on sequence is why I started here: it is not a minor setup task. It decides whether the cells are usable before the machine asks anything of them.

A commonly cited DDR2 example refreshes 8,192 rows within 64 milliseconds, or roughly once every 7.8 microseconds. Above 85 C, the maximum interval is halved. Those figures describe normal operation, not one company's boot sequence, but they show why a startup sequence is worth watching: refresh takes time and power.

August 27, 2026

That is why I noticed a cluster of dates last August. On August 21, the Shanghai Stock Exchange accepted Yangtze Memory Technologies' prospectus. Six days later, on August 27, a U.S. application assigned to the company, usually called YMTC, was published: US20260253629A1. It was filed on October 20, 2025 and claims priority from a Chinese application filed February 24, 2025. The calendar does not prove a strategic connection. It does show a memory maker putting an early stage of DRAM operation into the public record during a week when its financing plans became public news.

A trade report says YMTC plans two new Wuhan fabs, each with capacity up to 100,000 wafers a month, and says half would move into DRAM manufacturing alongside joint high-bandwidth memory development. Another report put YMTC at 14 percent of global NAND bit shipments in the second quarter of 2026, while a domestic rival, ChangXin, was growing fast in DRAM. Those reports are context, not a forecast, as I see them. They show that boot-time DRAM reliability is no longer a peripheral subject for a company best known for NAND.

Before the word lines

US20260253629A1 is modest in scope but precise about the moment it controls. It describes a memory array and supporting circuitry. After power-on, an initializing circuit starts the device, a signal-generating circuit directs a refreshing circuit, and every memory cell is refreshed at least once during initialization. The timing matters: that full refresh comes before the word-line configuration stage.

The filing presents this ordering as a way to let reads and writes begin without a separate time penalty. The proposed sequence is meant, in my more cautious reading, to fold refresh into work that must happen anyway. It is an on-chip coordination arrangement: the device generates the relevant refresh action during its own initialization rather than waiting for a later command.

A 2001 boot sequence

A U.S. patent issued in 2001, based on a 1999 filing, describes an SDRAM power-on sequence under the industry rules of its day: a 200-microsecond stabilization wait, precharging all banks, and at least two auto-refresh commands before the mode register is set. In other words, refreshing during initialization is not a new thought. The public material doesn't let me judge the legal validity of YMTC's claims, and publication is not a grant. But that older record changes how I read this one. The possible contribution is the automatic all-cell refresh arrangement and its placement before word-line configuration, not the bare idea that memory needs refresh at boot.

Where the risk actually sits

Boot reliability is only one reason the refresh schedule matters. Row-hammer research has repeatedly shown that activity near a row can disturb neighboring cells, and published work has bypassed refresh-based mitigations across generations. This filing isn't a row-hammer defense, as I read it. Nothing in the described arrangement promises that. Still, it belongs to the same set of timing questions: deciding precisely when, and how completely, dynamic memory is refreshed.

That is where I resist the grander reading. A power-on all-cell refresh may remove a startup delay, but it does not settle the hard problem of keeping billions of cells reliable over temperature, time, heavy use, and attack. ChangXin's Chinese patent, granted the day after the U.S. application assigned to YMTC was published, takes a different route: it stores addresses for cells with poor charge retention and loads them at power-on so they receive extra attention during every all-bank refresh. Together, the filings suggest a practical contest over boot-time control, not a sudden invention of refresh itself. The risk in these first milliseconds is plain: a small sequencing decision can become a question of data integrity, performance, and who owns a necessary implementation.

Sources

Reporting for this piece drew on the published filing and the references below.

The record, briefly. US20260253629A1, “Memory Devices, Operation Methods Of The Memory Devices And Memory Systems” A memory device includes a memory array and peripheral circuit. After power-on, an initializing circuit initializes the device, and a signal generating circuit directs a refreshing circuit to refresh all memory cells at least once during initialization.

More angles on this

A Sideways Reading of Split StaircasesAnother reading from the same G11C classification family, static stores.
CPC G11C: Static storesThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
Liquid Cooling Heat Dissipation Device For Multi-Disk Drive System Marks a Pause Worth NoticingAnother reading from the neighbouring G11B classification family, information storage based on relative movement between record carrier and transducer.
When a Vehicle Notices Something, Who Decides What the Moment Means?Another reading from the wider G06V classification family, image or video recognition or understanding.
When a Container Knows the Difference Between Open and FinishedAnother reading in the same Objects category on this site.

Read around this one:Public patent record USPTO published figure