Field Notes

When an Erase Setting Becomes a Timing Promise

A new erase-timing filing matters less for its novelty than for what it reveals about the increasingly expensive effort to keep NAND flash moving.

Clay-diorama editorial illustration related to Non-Volatile Memory Erase Scheme.

What changes in this design

Without this timing detail, a reader might assume that an erase command makes every involved part of memory start erasing at the same time.

Instead, it applies one or more erase pulses to separate sections of the row-selecting control wires at different times. It gradually adjusts those word lines so erasure starts in one section while another has not started.

This is worth knowing because the focus is not simply erasing memory, but controlling when erasure starts in its separate sections.

A $229 million verdict

On July 16, 2026, a federal jury in Waco, Texas awarded $229 million in a dispute over error-correction technology used in NAND flash products. That case was not about erasing memory cells, but it puts a hard number on a fact engineers already live with: small decisions deep inside flash chips can carry very large legal stakes.

With $229 million in view, I read US20260253643A1 less as a product announcement than as evidence of an expensive, persistent struggle. Ordinary device owners will never notice a newly published proposal for timing erase pulses across sections of a memory chip until storage stops improving.

A delayed voltage pulse

The filing's central move is to make different word-line segments wait on one another. A controller receives an erase command, applies one or more erase pulses to segments at different times, and ramps their word lines so erasure can begin in one segment without beginning in another.

At first, the delay sounds almost too modest to matter. Yet staggered erase comes with a cost: each segment needs its own voltage ramp-up, so the operation can be slower than a single pulse unless the timing is compensated. Here is the tension that kept drawing me back: a clever circuit arrangement meets the demand to erase quickly.

The 2004 paper trail

That tension was old long before this publication appeared. Spansion filed a flash-memory patent in 2004 for a variable-ramp-rate erase-pulse scheme. Its patent reported cutting pre-programming time from about 400 milliseconds to about 100 milliseconds, a 75 percent reduction, and it was granted in 2006.

SanDisk filed a later patent in 2021 for adaptive erase-time compensation in segmented erase, then received a grant in 2023. It describes the same broad engineering problem: pulses divided across word-line segments incur separate ramp time, so the system must claw some of that time back. Calling the new filing unimportant would be wrong, I think. It makes novelty the wrong first question.

No public source I could independently confirm established the new publication's assignee or inventors. An attribution gap matters. Calling this a SanDisk filing merely because a related SanDisk patent occupies nearby technical ground would be careless.

Six hundred and thirty word lines

Meanwhile, the underlying physics is becoming less forgiving. Kioxia reports that conventional erase performance starts to degrade around 630 word lines in taller 3D NAND stacks. Its researchers developed a different source-contact structure to sustain erase performance beyond 1,000 word lines, reporting more than 1,000 times the hole current.

Nothing in the new filing claims to repair that source-contact problem, and we should not read it as if it does. Carefully scheduled pulses may, in my view, buy needed control while the physical margin for erasing is shrinking. Commercially, it can matter without curing the bottleneck.

Forty trillion won

The business backdrop makes that distinction sharper. On August 19, 2026, a financial-news report described a South Korean memory maker's 40 trillion won, or $28.6 billion, share buyback as the largest in South Korean corporate history. The report also put SanDisk's gain for 2026 to that point at 585 percent, while another major memory maker's fiscal third-quarter revenue was $41.46 billion, up 345.7 percent year over year.

No valuation of this publication appears in that report, and I found no basis for pretending that it does. Still, those figures show why minute changes in erase control are not merely lab work in a period of intense money and attention. For me, the context was sobering: the rewards are large enough that a few well-placed claims can become part of a serious business fight.

Where the risk actually sits

This filing will not overturn flash memory. Instead, the sources point toward the opposite conclusion: erase-pulse timing has attracted patents for decades, and this publication enters a dense line of incremental work. Any judgment about whether its claims are new would require a claim-by-claim comparison with earlier disclosures. We have not done that comparison here.

For readers, the more useful question is what this persistence tells us. A short interval of extra control can be a genuine engineering gain, a point of patentable distinction, and still only a way to postpone a deeper limitation. What stays with me is not that this filing changes flash. Flash is being asked to improve under pressure from physics, competition, and courts at the same time.

Sources

Reporting for this piece drew on the published filing and the references below.

The record, briefly. US20260253643A1, “Non-Volatile Memory Erase Scheme” A memory controller receives an erase command and applies one or more erase pulses to word-line segments at different times, ramping their word lines so erasure begins at one segment without beginning at another.

More angles on this

At the Switch, Selective Erase Becomes a Question of ResponsibilityAnother reading from the same G11C classification family, static stores.
Non-Volatile Memory With Distributed Write: the erase step that sets the priceAnother reading from the same G11C classification family, static stores.
CPC G11C: Static storesThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
CPC G06F: Electric digital data processingThe official classification family this record was filed into, published in the USPTO Cooperative Patent Classification scheme.
The Light Loop Inside an Oral-Care RoutineAnother reading from the neighbouring G06T classification family, image data processing or generation, in general.

Read around this one:Public patent record USPTO published figure